Normally-off HEMT transistor with selective generation of 2DEG channel, and manufacturing method thereof

A normally - off HEMT transistor includes a heterostructure including a channel layer and a barrier layer on the channel layer ; a 2DEG layer in the heterostructure ; an insulation layer in contact with a first region of the barrier layer ; and a gate electrode through the whole thickness of the insula tion layer , terminating in contact with a second region of the barrier layer . The barrier layer and the insulation layer have a mismatch of the lattice constant ( " lattice mismatch ” ) , which generates a mechanical stress solely in the first region of the barrier layer , giving rise to a first concentration of electrons in a first portion of the two - dimensional conduc tion channel which is under the first region of the barrier layer which is greater than a second concentration of elec trons in a second portion of the two - dimensional conduction channel which is under the second region of the barrier layer .