The dielectric breakdown (BD) of thermal oxide (SiO) grown on cubic silicon carbide (3C-SiC) was investigated comparing the electrical behavior of macroscopic metal-oxidesemiconductor (MOS) capacitors with nanoscale current and capacitance mapping using conductive atomic force (C-AFM) and scanning capacitance microscopy (SCM). Spatially resolved statistics of the oxide BD events by C-AFM revealed that the extrinsic premature BD is correlated to the presence of peculiar extended defects, the anti-phase boundaries (APBs), in the 3C-SiC layer. SCM analyses showed a larger carrier density at the stacking faults (SFs) the 3C-SiC, that can be explained by a locally enhanced density of states in the conduction band. On the other hand, a local increase of minority carriers concentration was deduced for APBs, indicating that they behave as conducting defects having also the possibility to trap positive charges. The results were explained with the local electric field enhancement in correspondence of positively charged defects.

The cubic polytype of SiC (3C-SiC) is the only one that can be grown on silicon substrate with the thickness required for targeted applications. However, the crystalline quality of 3C-SiC on silicon has to be improved in order to benefit from the intrinsic 3C-SiC properties. In this project new approaches for the reduction of defects will be used and new compliance substrates that can help to reduce the stress and the defect density at the same time will be explored. Numerical simulations will be applied to optimize growth conditions and reduce stress in the material. The structure of the final devices will be simulated using the appropriated numerical tools where new numerical model will be introduced to take into account the properties of the new material. Thanks to these simulations tools and the new material with low defect density, several devices that can work at high power and with low power consumption will be realized within the project.

Progetto ENIAC III call The proposal aims to make EU independent from other developed countries on wide band gap semiconductors high quality material, equipment and advanced processing. This field is of strategic importance since it involves the development of high efficient systems (of high revenue) for applications whenever an electric power is needed: from telecommunication to automotive, from consumer electronics to electrical household appliances, from industrial applications to home automation. In particular, the consortium will develop an European technology including equipments (growth, processing and characterization), processing (growth and device fabrication) and characterization (methods and equipments) till some of the possible applications. The know how will be developed taking advantage of the presence of the most advanced public research centres and reference Universities operating on SiC and GaN technologies , large companies world leaders and many SME from 6 EU countries. 150mm 4H-SiC wafers of high quality are target establishing EU beyond the world wide state of the art, to date at 100mm wafers. Also GaN heteroepitaxy on 150mm Si wafers is considered.