We report on the fabrication and characterization of Schottky barrier transistors on polycrystalline silicon. The transistors were realized exploiting Cr-Si and Ti-Si Schottky barrier with a low thermal budget process, compatible with polymeric, ultraflexible substrates. We obtained devices with threshold voltages as low as 1.7 V (for n channel) and 4 V (for p channel) with channel lengths ranging from 2 to 40 um. Resulting on/off ratios are as high as 5 *10^3. The devices showed threshold voltages and subthreshold slopes comparable with already published N- and P-MOS devices realized with the same process on polyimide substrates thus representing a cheaper and scalable alternative to ultraflexible transistors with doped source and drain.

Different approaches to fabricate low-temperature polycrystalline silicon (LTPS) thin film transistors (TFTs) on polymer substrates are reviewed and the two main routes are discussed: (1) standard fabrication of LTPS TFTs on glass substrates followed by a transfer process of the devices on the polymeric substrate; (2) direct fabrication of the devices on the polymeric substrate. Among the different techniques we have described in more detail the process we have recently developed for the fabrication of LTPS TFTs directly on ultra-thin polyimide (PI) substrate. LTPS TFT technology is particularly suited for high performance flexible electronics applications, due to the excellent device characteristics, good electrical stability and CMOS technology. Flexible display application remains the most attractive application for LTPS technology, especially for AMOLED displays, where device stability and the possibility to integrate the driving circuits make LTPS technology superior to all the other competitive TFT technologies. Among the other applications, particularly promising is also the application to flexible smart sensors, where integration of a front-end electronics is essential. Some examples of flexible gas sensors and pressure sensors, integrated with simple readout electronics based on LTPS TFTs and fabricated on ultra-thin PI substrate, are presented. © 2012 Elsevier Ltd.

In this work we present a study of the electrical stability of self-aligned p-channel TFTs fabricated using excimer laser annealing. The electrical stability was tested performing bias stress experiments and accelerated stability tests and we found that the device characteristics were seriously degraded upon application of large negative gate bias. From extensive analysis of the phenomenon through numerical simulations, we found that the device degradation could be perfectly reproduced by positive charge injection into the gate oxide in narrow (300-400 nm) regions at the edges of the gate, near the source and drain contacts. From the present results we conclude that the observed degradation is closely related to the residual damage, induced by ion implantation, present in the gate oxide near the gate edges. © 2007 Elsevier Ltd. All rights reserved.

In this work we present the electrical characterization of non self-aligned p-channel thin film transistors fabricated by using laser doping technique for source/drain contact formation and gate oxide deposited at room temperature by Electron Cyclotron Resonance Plasma Enhanced Chemical Vapour Deposition. These techniques are suitable for a very low temperature process for TFT fabrication. The output characteristics show a current increase at high drain voltage, (bkinkQ effect) rather moderate, if compared to self aligned polysilicon TFTs, probably due to the gradual doping profile induced by laser doping process. After bias stress at low gate voltage and high drain voltage condition a strong reduction of kink current has been observed in the output characteristics at high drain voltage, whereas minor changes has been observed in the transfer characteristics. This behaviour is similar to what observed in n-channel Gate Overlapped Thin Film Transistors. In the high gate voltage and high drain voltage bias-stress condition we observed only a rigid shift of the transfer characteristics probably related to charge injection in the gate oxide, while subthreshold slope remains constant.

Low-frequency noise has been investigated in self-aligned ?SA. and gate overlapped lightly doped drain ?GOLDD. polysilicon thin-film transistors ?TFTs.. We found that, at low Vds, both device structures are characterised by 1f noise, originating from carrier number fluctuations. However, when the SA devices were operated in the kink regime, an excess noise was observed, in contrast to GOLDD TFTs. This has been explained by attributing the excess noise to supplemental oxide charge fluctuations induced by hot-carrier injection into the gate oxide. By using two-dimensional numerical simulations, we show that the hot-electron emission current in SA polysilicon TFTs is much higher than in the GOLDD structure.

In high performance polysilicon thin film transistors ?TFTs. the uniformity of electrical characteristics remain a major problem. This situation has stimulated a growing activity aiming to control the lateral growth phenomenon. However, most of the techniques require additional processing steps or a rather high shot density. We present a technique based on a two-pass excimer laser crystallization process: during the first irradiation the sample is irradiated through a patterned mask, while the second irradiation, performed without the mask, results in the homogeneous crystallization of the sample. This technique allows the possibility of forming uniform polysilicon layers, with large ?;2 micron. and aligned grains, with a reduced number of shots and a relatively large process energy window. The results of crystallization performed at different laser energy densities, sample thickness and laser pulse duration are analyzed.

The introduction of excimer laser crystallization ELC. techniques in the fabrication of polysilicon thin-film transistors TFTs. has produced a tremendous improvement in the device characteristics. When the Super Lateral Growth SLG. mechanism is triggered, large )1 mm. grains are formed and this crystallization regime appears very attractive from the device fabrication point of view. In fact, using SLG-polysilicon active layers high performance electron field-effect mobility)300 cm2rV s. TFTs can be obtained and a detailed analysis of the electrical characteristics of such devices is presented. However, the SLG mechanism has a very narrow energy density window and, consequently, highly uniform beam profiles and pulse-to-pulse stability better than 2% are required. This implies that standard ELC-process is technologically quite critical and several approaches have been proposed to improve the process uniformity. Among these we will discuss three main techniques: 1. the use of opportunely semi-gaussian. profiled beams; 2. the combined use of Solid Phase Crystallization SPC. and ELC techniques; 3. control of the lateral growth. In particular, we present a novel technique to control the lateral growth, based on a two-pass ELC-process. The proposed technique can be rather attractive for polysilicon TFT fabrication, allowing a precise grain location control through the mask geometry. and being characterized by a few 3-5. laser shots process and wide energy density windows.