Articolo in rivista, 2008, ENG, 10.1016/j.sse.2007.10.009

Electrical instability in self-aligned p-channel polysilicon TFTs related to damaged regions present at the gate edges

Rapisarda, Matteo; Mariucci, Luigi; Valletta, Antonio; Pecora, Alessandro; Fortunato, Guglielmo; Caligiore, C.; Fontana, Enzo; Leonardi, Salvatore; Tramontana, Francesca

Institute for Photonics and Nanotechnologies, Rome; STMicroelectronics

In this work we present a study of the electrical stability of self-aligned p-channel TFTs fabricated using excimer laser annealing. The electrical stability was tested performing bias stress experiments and accelerated stability tests and we found that the device characteristics were seriously degraded upon application of large negative gate bias. From extensive analysis of the phenomenon through numerical simulations, we found that the device degradation could be perfectly reproduced by positive charge injection into the gate oxide in narrow (300-400 nm) regions at the edges of the gate, near the source and drain contacts. From the present results we conclude that the observed degradation is closely related to the residual damage, induced by ion implantation, present in the gate oxide near the gate edges. © 2007 Elsevier Ltd. All rights reserved.

Solid-state electronics 52 (3), pp. 406–411

Keywords

Bias stress, Electrical stability, Polycrystalline silicon, Thin film transistors

CNR authors

Rapisarda Matteo, Mariucci Luigi, Pecora Alessandro, Fortunato Guglielmo, Valletta Antonio

CNR institutes