In this paper we analyze the effect of the top metal overlap associated to the drain contact, that can be present in thin film transistors (TFTs) with bottom-gate staggered configuration. It is shown that the effect of the top metal contact at the drain, overlapping the passivation or etch stopper layer (ESL), increases the drain current. Results from numerical simulations show that this top metal overlap acts as a second gate to the device, partially located near the drain contact. The overall effect on the device current will depend on the semiconductor doping, as well as on the thickness and dielectric constants of the gate dielectric and passivation/ESL layers. The effect is more significant as the channel length of the devices is reduced.

--In this work we report on the results of DirectCurrent (DC) and Low-Frequency Noise (LFN) measurements in p-type staggered top-gate Organic Thin-Film-Transistors (OTFTs). The analysis involves the effects of Source/Drain contacts and the stability characteristics of OTFTs induced by Gate and Drain bias stress. Noise data are interpreted in the context of a multi-trap correlated-mobility-fluctuations (CMFs) model, showing that noise is dominated by acceptor-like traps. The influence of noise sources at contacts is found to be negligible. However contacts affect the measured noise by a non negligible differential resistance. The product between the scattering parameter and the effective mobility DPeff?2?107 cm2/C, which measures the strength of CMFs, is similar to what reported for a-Si:H and much higher with respect to c-Si MOSFETs revealing a strong correlation between CMFs and the state of disorder of the active layer. Instability is observed in presence of Drain bias stress and for sufficient short channel length (<10Pm). The measured shift in LFNMs appears correlated with the shift of the measured channel current. In the context of the CMF model the noise shift can be interpreted as due to the increase of DPeff caused by the increased scattering between the charged channel carriers and the charged traps at the interface.

In this work, staggered top-gate n-type organic thin film transistors (OTFTs) with evaporated PDIF-CN2 semi-conducting layers, spin-coated Cytop (TM) dielectric barriers and channel lengths ranging from 100 to 2 mu m were fabricated on polyethylene-naphtalate (PEN) substrates. Hexamethyldisilazane (HMDS) treatment of the PEN surface was successfully tested as an effective strategy to achieve flexible devices with improved electrical response. Following this approach, maximum field-effect mobility (mu(FE)) values exceeding 0.4 cm(2)/V.s were observed in air. Moreover, the self-encapsulating features of the investigated top-gate configuration, employing the highly hydrophobic Cytop (TM) dielectric films, allowed getting considerable performances in terms of un-sensitivity to hysteresis and bias stress phenomena.

Organic material deposition by gravure printing is a promising pathway for the realization of large area flexible electronic devices. Nevertheless, in order to achieve high performance it is required to improve the electronic ink printability, operating on the fluid dynamic mechanisms involved during the process. In this work, this issue has been faced working on ink characteristics for a conductive and a dielectric material. The suitable ink features have been defined studying the influence on the printability of the different forces that act in the fluid during the printing process, using an experimental approach. Properly defined ink formulations have been printed, considering different shapes and dimensions of the cells on the gravure cliche to fit the ink features. The printing outcomes have been compared and analysed through the evaluation of several significant fluid dynamic parameters and the rheological characterization of the materials. Finally, exploiting the results of this study, high performance fully printed organic thin film transistors have been realized.

Here, electron-transporting semiconducting organic channels made of N,N?-1H, 1H-perfluorobutyl dicyanoperylenecarboxydiimmide (PDIF-CN2) molecules were thermally evaporated on flexible polyethylene-naphtalate (PEN) plastic substrates equipped with gold (Au) electrodes. This multilayer structure represents the basic component for the fabrication of staggered top-gate n-type organic thin-film transistors (OTFTs) to be completed with the addition of a polymeric dielectric layer and an aluminum gate electrode. PEN substrate was treated with hexamethyldisilazane (HMDS) in order to make it more hydrophobic. Indeed, the hydrophobized surface of the plastic substrate was shown to induce a more ordered supramolecular structure of the semiconductor layer during the evaporation process. The hybrid organic/inorganic formally trilayer non-passivated OTFT structure was successfully profiled in a single run through ToF-SIMS depth profiling experiments with low energy cesium ions. High mass molecular fragment ions were obtained and used as indicators of interfaces, leading to an increase of information on molecular specificity. The HMDS surface modification was clearly detected and spatially located. Finally, a chemometric approach was also adopted to evaluate depth profiling data. In particular, principal component analysis (PCA) and K-means algorithm were tested as innovative method for the identification of molecular fragments useful for the OTFT multi-layer structure characterization and the determination of the number of OTFT layers, respectively

In this work, staggered top-gate n-type organic thin film transistors (OTFTs) with evaporated PDIF-CN2 semiconducting layers, spin-coated Cytop(TM) dielectric barriers and channel lengths ranging from 100 to 2 ?m were fabricated on polyethylene-naphtalate (PEN) substrates. Hexamethyldisilazane (HMDS) treatment of the PEN surface was successfully tested as an effective strategy to achieve flexible devices with improved electrical response. Following this approach, maximum field-effect mobility (?FE) values exceeding 0.4 cm2/V?s were observed in air. Moreover, the self-encapsulating features of the investigated top-gate configuration, employing the highly hydrophobic Cytop(TM) dielectric films, allowed getting considerable performances in terms of un-sensitivity to hysteresis and bias stress phenomena

We present a compact model for the DC and small signal AC analysis of Organic Thin Film Transistors (OTFTs). The DC part of the model assumes that the electrical current injected in the OTFT is limited by the presence of a metal/organic semiconductor junction that, at source, acts as a reverse biased Schottky junction. By including this junction, modeled as a reverse biased gated diode at source, the DC model is able to reproduce the scaling of the electrical characteristics even for short channel devices.

This work introduces a compact DC model developed for organic thin film transistors (OTFTs) and its SPICE implementation. The model relies on a modified version of the gradual channel approximation that takes into account the contact effects, occurring at nonohmic metal/organic semiconductor junctions, modeling them as reverse biased Schottky diodes. The model also comprises channel length modulation and scalability of drain current with respect to channel length. To show the suitability of the model, we used it to design an inverter and a ring oscillator circuit. Furthermore, an experimental validation of the OTFTs has been done at the level of the single device as well as with a discrete-component setup based on two OTFTs connected into an inverter configuration. The experimental tests were based on OTFTs that use small molecules in binder matrix as an active layer. The experimental data on the fabricated devices have been found in good agreement with SPICE simulation results, paving the way to the use of the model and the device for the design of OTFT-based integrated circuits.

Investigation of gate dielectric conduction properties in organic p-type staggered thin-film transistors is reported by means of direct-current, capacitance-voltage, and noise measurements. Results suggest that transport in the CYTOP (TM) gate dielectric is dominated, at low currents, by Schottky conduction due to the emission at the aluminum gate interface through a barrier phi(B) approximate to 1 eV, while is limited, at higher currents, by space-charge conduction in the trap-limited regime with an effective mobility mu(theta) estimated in the order of 10(-9) cm(2)/(Vs). Gate current noise follows a 1/f law and it is found to be proportional to I-G(2), which is inconsistent with the commonly assumed mobility fluctuation. Traps responsible for gate noise are dielectric-bulk traps, not located at the semiconductor interface, since the gate noise is found to be uncorrelated with drain noise.

As fabrication and positioning of micro- and nanocrystals grow in importance in a wide range technological applications, there is an increasing requirement for the development of a shared technological platform that is able to process materials from solutions on large areas. Here, the application of lithographically controlled wetting (LCW) for the manipulation and positioning of single crystals directly on devices is reported. In the LCW, a stamp, consisting of a metallic grid, is positioned in contact with a liquid thin film spread on a substrate; under these conditions, the capillary forces pin the solution to the stamp protrusions, thus splitting the continuous film in separated droplets or channels. As the solvent evaporates and the solution reaches the saturation, the solute precipitates onto the substrate within the menisci, giving rise to a structured thin film, in correspondence of the protrusion of the stamp. The possibility to achieve a patterning of crystals of conjugated molecules with a defined shape and with controlled size directly on device is demonstrated and pattern of crystals are investigated using polarized optical microscopy, atomic force microscopy, X-ray diffraction; they are also electrically characterized.

We studied, by 2D numerical simulations, the effects of poor semiconductor morphology near the source and drain contacts of BGBC-OTFTs. The variations of the electrical characteristics and of the path of the injected carriers in the transistor channel have been analyzed considering different defective regions, parameters (mobility, density of states) and contact thicknesses. The results showed that 100 nm wide defective regions can induce high contact resistance, resulting in large variation in the electrical characteristics. However, the typical S-shape in the low-Vds output characteristics is clearly observed only considering a combination of highly defected regions and Schottky barrier at the contacts. Furthermore, the simulations showed that most of the current is injected and extracted, at the source and drain contact, within a few nanometers from the semiconductor- dielectric interface. This explains the small influence of the contact thickness on the simulated electrical characteristics, at least for a contact thickness down to 10 nm.

We propose the implementation of graphene-based field effect transistor (FET) as radiation sensor. In the proposed detector, graphene obtained via chemical vapor deposition is integrated into a Si-based field effect device as the gate readout electrode, able to sense any change in the field distribution induced by ionization in the underneath absorber, because of the strong variation in the graphene conductivity close to the charge neutrality point. Different 2-dimensional layered materials can be envisaged in this kind of device.

Low-frequency noise (LFN) has been used in order to gain insight into the physical properties of the materials involved in organic thin-film transistors (OTFTs) fabrication, often with contradictory results. Besides the physical origin of noise, contact effects on noise have been a source of concern and discussion. In this paper, we report on accurate LFN measurements in p-type staggered top-gate OTFTs over four decades of channel current, from the subthreshold to the strong accumulation region. The measured spectra follow a clear 1/$f$ behavior attributed to the trapping/detrapping of channel charge carriers into interface and oxide defects, while the influence of noise sources at contacts is found to be negligible. However, contacts affect the measured noise by a nonnegligible differential resistance. Noise data are interpreted in the context of a multitrap correlated mobility fluctuations (CMFs) model, showing that noise is dominated by acceptor-like traps. Despite the low mobility (?eff ~ 2 cm²/V/s), the large scattering parameter (? ~ 10? Vs/C) produces an increase of the noise at the higher currents due to CMFs. The product ??eff ? 2·10? cm²/C, which measures the strength of CMFs, is similar to what was reported for a-Si:H and much higher with respect to crystalline silicon MOSFETs revealing a strong correlation between CMFs and the state of disorder of the active layer.

We have investigated the stability of the electrical performances in staggered organic thin film transistors (OTFTs) manufactured by using a CYTOP fluoropolymer as a gate dielectric, after the devices underwent reliability cycles in a high moisture and temperature controlled environment chamber. The results of such testing cycles showed a very high stability against the environmental conditions that might be related to the device top-gate structure, working as an efficient encapsulation, and to the hydrophobic properties of the fluoropolymer used as gate dielectric.

A unified drain current model of complementary (p- and n-type) organic thin film transistors (OTFTs) is presented. The model is physically based and takes into account the detailed properties of the organic semiconductor through the density of states (DOS). The drain current depends on the geometrical and physical parameters of the transistor, on the applied gate, drain and source voltages, and on the surface potential at the source and drain contacts. An analytical expression of the surface potential is derived. The proposed model is validated with the numerical calculations and the measurements of both p- and n-type OTFTs fabricated in a printed complementary technology. The provided analyses show that the model is continuous, accurate, and includes the main physical effects taking place in complementary organic transistors. Thanks to its analytical and symmetric formulation, it is suitable for the design of organic integrated circuits. Moreover, the unified physical picture provided by the model enables the extraction of the OTFTs physical parameters, thus it is a very powerful tool for the technology characterization.

We report on the results of noise measurements in ptype organic thin-film transistors (OTFTs) extending from the subthreshold region into the strong accumulation region over four decades of drain current values. The low frequency noise produced by the devices can be successfully interpreted in the context of the multi-trap correlated number fluctuation - mobility fluctuation (CMF) theory, while neither phonon induced mobility fluctuation nor carrier number fluctuation mechanisms are capable of justifying the observed noise behavior. The Coulomb scattering parameter is found to be in the order of 107 Vs/C, about three orders of magnitude larger with respect to crystalline Silicon (c-Si) MOSFETs and comparable to what already reported in hydrogenated amorphous silicon (a-Si:H) TFTs, suggesting a much more relevant contribution coming from CMF in disordered materials.

Organic thin-film transistors (OTFTs) are an emerging technology for large scale circuit integration, owing the availability of both p- and n- channel devices. For the technology development and the design of circuits and digital systems, the accurate physical modeling is mandatory. In this work we propose an unified analytical model for both p- and n- type OTFTs. The model is physically based and accounts for a double exponential density of states (DOS). It is simple, symmetric and accurately describes the below-threshold, linear, and saturation regimes via a unique formulation. The model is eventually validated with the measurements of complementary OTFTs fabricated in a fullyprinted technology.

Nowadays organic electronics can be successfully adopted as an enabling technology for the development of a new generation of smart flexible sensors. In fact the ceaseless progress concerning organic materials and low cost fabrication technologies is pushing organic electronics towards applications difficult to conceive only a few years ago. In particular, in robotics, where the development of tactile sensor array is a critical issue, flexible sensing techniques based on new materials result mostly appealing for the fabrication of electronic skin. Tactile sensing can enhance the cognitive input that a robot can collect for acquiring fundamental information of the environment in which the robot is operating [1-3]. In this work we investigated flexible tactile sensors fabricated by integrating an ultrathin piezoelectric capacitor based on PVDF-TrFE film with an OTFT made on a PEN substrate by using a multi-foil approach [4-5] (see fig.1). The sensing element is a non-coplanar circular structure with an area of 2 mm2 and the thickness of PVDF-TrFE is 2 um. The sensor has been fabricated on a flexible polyimide substrate reaching a final thickness of 7 um. P-channel OTFTs, with staggered top-gate configuration were fabricated on a PEN foil, 125 um thick, adopting the following materials: 1) evaporated gold for source-drain contacts; 2) solution processed pentacene derivative, namely SmartKem? p-FLEX(TM) supplied by SmartKem Ltd, about 30nm thick, as organic semiconductor; 3) a fluoropolymer (CYTOP) film, 500nm thick as gate dielectric; 4)aluminium as gate electrode. The active material and the dielectric were deposited by spin-coating technique and lithographically patterned. The OTFTs dimensions were designed ranging from 2 to100 um as channel length and 50, 100 and 200 um as channel width. The devices show very high performance with field effect mobility up to 3cm2/Vs, low threshold voltages (0.2 V) and sub-threshold slope (2 V/dec) and excellent stability, making them good candidates to drive a sensing system. The sensor was then mounted on a flexible PCB and inserted into a mini-shaker to measure its response at different mechanical stimuli in terms of applied force (up to 3 N) and working frequency (up to 1.1 kHz). The device was analysed in thickness mode, thus exploiting the higher piezoelectric coefficient d33 that for PVDF-TrFE is of about 30 pC/N. The sensor was then connected in a common-source amplifier configuration by using a load resistance of 8 MOhm. Due to the non negligible value of the impedance used in the circuit the output signal was read through a trans-resistance amplifier (see Fig.2) placed on the source terminal of the DUT. Virtual ground has been set at the input to make a more reliable measure. The linear response of the sensor measured for a sinusoidal stimulus at 200 Hz is shown in fig.3. The offset of about 10mV has been verified to be due to an internal offset of the trans-resistance amplifier only. In fig.4 the behaviour of the sensor at increasing working frequencies is analysed for an incoming stimulus of 1 N. The output increases with the frequency due to the circuital high-pass filter composed by CPVDF-TrFE and RGG at the gate

Instability induced by gate bias stress and light exposure have been investigated in organic thin film transistors made on flexible plastic substrate. P-channel OTFTs, with staggered top-gate configuration were fabricated on PEN, 125?m thick, using: evaporated gold for source-drain contacts; solution-processed pentacene derivative, (SmartKem? p-FLEX(TM) by SmartKem-Ltd), 30nm thick, as organic semiconductor; fluoro-polymer (CYTOP) film, 500nm thick as gate dielectric; aluminium as gate electrode. The active material and the dielectric were spin-coated and lithographically patterned. OTFTs channel lengths ranged from 2 to 100?m. Devices showed high field-effect mobility (up to 3 cm2/Vs), low threshold voltage (~-5V) and sub-threshold slope (~1V/dec). In order to test electrical stability of the devices, gate bias-stress at high |Vgs| (-40 V) has been performed, both at RT (vacuum and air) and at substrate temperature up to 330K (vacuum only), for long bias stress times (up to 80ks), monitoring the transfer characteristics of the devices at selected times. Excellent electrical stability was found: the characteristics showed no degradation during gate bias stress performed at RT in vacuum (both in linear and sub-threshold regime), while small positive threshold voltage shift (~0.5V) was observed during experiments performed in air and at high T. The very high stability of the devices under gate polarization allows us to investigate the effects of illumination on the electrical characteristics. Illumination produced right shift of the characteristics, mainly in the sub-threshold regime (several volts), while the on-regime was less affected (small VT variation). When devices were stored in dark without polarization, characteristics fully recovered, with relaxation time of the order of 100ks, depending on substrate temperature. In order to analyse this phenomenon, we monitored the relaxation dynamics during dark relaxation changing the light intensity and duration, light wavelength, gate polarization during illumination and substrate temperature during dark relaxation. To explain the experimental data, different mechanisms, including charge trapping and metastable defect creation, are considered and a model that describes the observed phenomena is presented.